1. Field of the Invention
The present invention relates to a liquid crystal display (LCD), and more particularly, to a thin film transistor (TFT) for an LCD (TFT-LCD) and a method for manufacturing the same.
2. Discussion of the Related Art
In an LCD of an active matrix using a TFT, each pixel, the unit of array, has a TFT and a pixel electrode. FIG. 1 shows a conventional pixel structure of an inverted-staggered TFT in which a pixel electrode and a drain electrode of a TFT are made of a same transparent conductive material In order to form such a structure, a gate electrode 11 is formed on a glass substrate 10, and a gate insulating layer 12 is formed thereon. Then, intrinsic amorphous silicon (a-Si:H) and doped amorphous silicon (n.sup.+ -a-Si:H) are formed sequentially and patterned to form an active layer 13 and an ohmic contact layer 14. A transparent conductive material is deposited on the overall surface of the substrate and patterned to form an integrally formed drain/pixel electrode 15. Subsequently, metal (Al) is deposited on the overall surface of the substrate and patterned to form a source electrode 16.
The portion of the ohmic contact layer 14 at the channel region is etched using the source/drain electrode as a mask. A surface passivation layer 17 is deposited on the overall surface of the substrate so that an inverted-staggered TFT is made. In this structure, the gate electrode 11 is placed over the glass substrate 10, the gate insulating layer 12 is placed over the gate electrode 11, the active layer 13 is formed over the gate insulating layer 12, arid the ohmic contact layer 14 is on both sides of active layer 13 excluding the channel region. An integrally formed drain/pixel electrode 15 (ITO) is formed on one side of the ohmic contact layer 14 and the gate insulating layer 12. The source electrode 16 is located on the other side of the ohmic contact layer 14. A surface passivation layer 17 is formed on the overall surface of the substrate.
FIG. 2 shows a pixel structure of a TFT-LCD having a self-aligned top gate, in which an active region 21 is formed of intrinsic polysilicon over glass substrate 20, and a gate insulating layer 23 is formed on the overall surface of the substrate including the active region 21. Then, a gate electrode 24 is formed on the gate insulating layer 23 over the active region 21. Ion implantation is performed using gate electrode 24 as a mask to form source and drain regions (S/D). An insulating material is formed on the overall surface of the substrate to form an interlevel insulating layer 25, and contact holes are formed in the interlevel insulating layer 25 and the gate insulating layer 23 at the source and drain regions (S/D).
A transparent conductive material is deposited in the contact hole and on the interlevel insulating layer 25, and patterned to integrally form drain/pixel electrode 26. Then, metal is deposited on the overall surface of the substrate and patterned to form a source electrode 27. A surface passivation layer 28 is formed on the overall surface of the substrate. The integrally formed drain/pixel electrode 26 is connected to drain region D via the contact hole formed thereon. The source electrode 27 is connected to source region S via the contact hole formed thereon.
In the pixel structures shown in FIGS. 1 and 2, the drain and pixel electrodes are formed of a single transparent conductive material, thereby simplifying the process. However, the source electrode (signal wire) is formed after the integrally formed drain/pixel electrode is formed. Here, metal (Al) is deposited on the overall surface of the substrate and patterned. Thus, the integrally formed drain/pixel electrode is easily damaged during the etching process of the metal. In particular, this damage is caused by a galvanic effect during wet etching and by plasma damage during dry etching. This results in poor device characteristic and unsatisfactory yield.